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FPU code generation

With BP 7.0, I wrote a procedure containing assembly opcodes for the
FPU. I noticed that the compiler inserts a WAIT instruction after each
FPU instruction. I read that this instruction is not necessary anymore
on newer processors (I possess a Pentium). Is that true, and if yes, how
can I prevent the compiler from generating the WAIT?
 

Re:FPU code generation


In article <3642EBB5.6F8C4...@rz-online.de>,

Quote
Frederic  <frede...@rz-online.de> wrote:
>With BP 7.0, I wrote a procedure containing assembly opcodes for the
>FPU. I noticed that the compiler inserts a WAIT instruction after each
>FPU instruction. I read that this instruction is not necessary anymore
>on newer processors (I possess a Pentium). Is that true, and if yes, how
>can I prevent the compiler from generating the WAIT?

Have you tried 286 code generation?

Osmo

Re:FPU code generation


On Fri, 06 Nov 1998 13:29:41 +0100, Frederic <frede...@rz-online.de>
wrote:

Quote
> With BP 7.0, I wrote a procedure containing assembly opcodes for the
> FPU. I noticed that the compiler inserts a WAIT instruction after each
> FPU instruction.

No. In front of each FPU instruction. This is a big difference.

Quote
> I read that this instruction is not necessary anymore
> on newer processors (I possess a Pentium). Is that true, and if yes, how
> can I prevent the compiler from generating the WAIT?

In a DOS or DPMI application you cannot prevent the compiler from
generating the WAIT prefix.

In fact the problem is a little bit different. BP doesn't generate
true FP opcodes at all (except for no-wait control instructions like
FNINIT beginning with FN...). It encodes them as an emulating
interrupt call. At run time (if a copro is present) the opcodes will
be patched by a patch module which hooks the relevant interrupts to
regular FPU opcodes before they are executed for the first time. As
the emulation opcode is always one byte longer than the regular FPU
opcode, the empty place is filled with a one byte WAIT instruction.
This WAIT is inserted _in_ _front_ of the FPU opcode.

        asm fldz end;

will compile to

        CD 35 EE   { int $33 , byte 2 of opcode }

this will be patched before the first execution to

        9B D9 EE   { WAIT  FLDZ }

On modern copros like yours this won't slow down the execution because
they automatically skip any WAIT in front of a
non-control-instruction, i.e. they don't _execute_ it - although the
opcode has to be read and decoded by the CPU - but this can't be
avoided, Well, only by writing external procedures with an assembler
and linking them into the program or by coding your FPU instructions
via db ;-)

By the way: TP6.0 has an undocumented quirk. If the switch {$G+} is
set, BASM would produce true opcodes without leading WAITs.

Quote
>--test.pas----<

{$N+,G+}
begin
  asm fldz end
end.

Quote
>--------------<
>---TP 6.0 -------------------<

PROGRAM.3:  asm fldz end                                    
  cs:000F D9EE           fldz                                
PROGRAM.4: end.                                              

Quote
>---TP 7.0 -------------------<

compiled code

PROGRAM.3:  asm fldz end                                    
  cs:000D CD35EE         fldz                                
PROGRAM.4: end.                                              

after run time patch

PROGRAM.3:  asm fldz end                                    
  cs:000D 9B             wait                                
  cs:000E D9EE           fldz                                
PROGRAM.4: end.                                              

Quote
>-----------------------------<

Regards
Horst

Re:FPU code generation


Osmo Ronkanen schrieb:

Quote
> Have you tried 286 code generation?

Strangely enough, now no WAITs are generated anymore, no matter which code
generation is used. Computers are a mystery.

Re:FPU code generation


On Fri, 06 Nov 1998 18:39:48 +0100, Frederic <frede...@rz-online.de>
wrote:

Quote
> Osmo Ronkanen schrieb:

> > Have you tried 286 code generation?

> Strangely enough, now no WAITs are generated anymore, no matter which code
> generation is used. Computers are a mystery.

Please show me an example where TP7.0 BP7.0 (this was your question)
won't produce WAITs.

Or did'nt you realize that the code

        CD33EE           fldz

which is produced by the FLDZ instruction and which is displayed by TD
as "fldz" is only an emulator-fldz (i.e. an interrupt call
CD33=int$33) which will change immediately to

        9A               wait
        D9EE             fldz

if you step through the instruction because the called interrupt
patches the code and executes it afterwards as 'wait fldz' ?

Regards
Horst

Re:FPU code generation


In article <3642EBB5.6F8C4...@rz-online.de>,
  Frederic <frede...@rz-online.de> wrote:

Quote
> With BP 7.0, I wrote a procedure containing assembly opcodes for the
> FPU. I noticed that the compiler inserts a WAIT instruction after each
> FPU instruction. I read that this instruction is not necessary anymore
> on newer processors (I possess a Pentium). Is that true, and if yes, how
> can I prevent the compiler from generating the WAIT?

First of all, the WAITs are put before the instructions. They are the result
of the run-time library coprocessor emulator replacing the emulated
instructions, if a real FPU is present, by real FPU instructions. In TP6 you
can generate "pure" FPU instructions using the G+ directive, except for these
ones:

FCLEX
FDISI
FENI
FINIT
FSTCW
FSTENV
FSAVE
FSTSW

(Use the FN.. ones)

AFAIK, TP/BP7 always generate emulated instructions, resulting in the WAIT.

However, by using Norbert Juffa's TPL60N19.ZIP or (I don't use it, so not
sure) BPL70N16.ZIP, you can get rid of the WAITs, but you'll get NOPs
instead.

HTH,

Robert
--
Robert AH Prins
prin...@williscorroon.com

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Re:FPU code generation


Horst Kraemer schrieb:

Quote
> Please show me an example where TP7.0 BP7.0 (this was your question)
> won't produce WAITs.

> Or did'nt you realize that the code

>         CD33EE           fldz

> which is produced by the FLDZ instruction and which is displayed by TD
> as "fldz" is only an emulator-fldz (i.e. an interrupt call
> CD33=int$33) which will change immediately to

>         9A               wait
>         D9EE             fldz

> if you step through the instruction because the called interrupt
> patches the code and executes it afterwards as 'wait fldz' ?

> Regards
> Horst

I read about this emulation technique only a few hours ago for the first time in
my short life. Sorry :-)

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